The present invention relates to an improvement of a phase synchronous circuit.
In recent years, with data communications speeded up and increasing in data quantity, and with microprocessors operating at higher speeds, an operating frequency of a synchronous circuit typified by a PLL (Phase Locked Loop) circuit has been increasingly getting high.
FIG. 7 illustrates a basic construction of a conventional PLL circuit. The PLL circuit is constructed of a phase comparator 11, a charge pump circuit 12, a low-pass filter 13, a VCO (Voltage Controlled Oscillator) 14 and a frequency-divider 15.
The phase comparator (including a phase frequency comparator) 11 detects a phase difference between a phase of a reference signal f.sub.s and a phase of a frequency dividing signal into which an output signal f.sub.out of the VCO 14 is frequency-divided by the frequency divider 15. If the phase of the frequency dividing signal is judged to be more delayed than the reference signal f.sub.s as a result of the detection, an up-signal UP is supplied to the charge pump circuit 12 for only a time proportional to the phase difference. Whereas if the phase of the frequency dividing signal is more advanced than the reference signal f.sub.e, a down-signal DN is supplied to the same circuit 12 for only the time proportional thereto. The up-signal UP is used for advancing the phase of the output signal f.sub.out outputted from the PLL circuit, while the down-signal DN is used for delaying the phase of the output signal f.sub.out outputted from the PLL circuit. Upon receiving these two up- and down-signals UP, DN from the phase comparator 11, the charge pump 12 flows electric charges into a capacitor of the low-pass filter 13 disposed posterior during a period when the up-signal remains active, but draws the electric charges out of the capacitor during a period when the down-signal remains active, thus performing the charging/discharging process. This charging/discharging process is integrated by the low-pass filter, and the low-pass filter 13 outputs an output voltage Vc corresponding to a quantity of the electric charges accumulated in the capacitor. The VCO 14 is supplied with this output voltage Vc as a voltage for controlling the oscillation frequency. The VCO 14 changes the oscillation frequency corresponding to this control voltage Vc, and feedback control is executed so that the phase of the output signal f.sub.out of the PLL circuit follows up the phase of the reference signal f.sub.s. Then, the frequency and the phase of the output signal f.sub.out generated by the PLL circuit coincide with the reference signal f.sub.s. This phase coincident state is called a lock state. Note that the frequency divider 15 is used when multiplying the reference signal f.sub.s and generating a signal of a synchronized high frequency.
When the frequency of the reference signal f.sub.s to be synchronized becomes high, an oscillation frequency band of the VCO 14 also heightens, resulting in an increase in gain (control voltage variation .DELTA.Vc versus output frequency variation .DELTA.f.sub.out) of the VCO 14. This is illustrated in FIG. 8 which describes characteristics of the conventional PLL circuit. As will be obvious from FIG. 8, if the oscillation frequency band of the VCO 14 is high, an oscillation range of the VCO 14 must be broadly covered in order to generate a signal having a desired frequency.
However, a fluctuation width of the control voltage Vc of the VCO 14 does not increase, and hence an inclination of oscillation characteristic of the VCO 14 becomes steep. This implies that a slight fluctuation in the control voltage Vc of the VCO 14 causes a large fluctuation in the oscillation frequency f.sub.out of the VCO 14, and therefore a durability of the PLL circuit against noises is to be deteriorated. Further, if a power supply voltage of the circuit decreases because of a reduction in consumption electric power, the fluctuation width of the control voltage Vc of the VCO 14 is narrowed, with the result that the oscillation range demanded of the VCO 14 can not be secured.